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LMH6505 Wideband, Low Power, Linear-in-dB, Variable Gain Amplifier
December 14, 2007
LMH6505 Wideband, Low Power, Linear-in-dB, Variable Gain Amplifier
General Description
The LMH6505 is a wideband DC coupled voltage controlled gain stage followed by a high speed current feedback operational amplifier which can directly drive a low impedance load. The gain adjustment range is 80 dB for up to 10 MHz which is accomplished by varying the gain control input voltage, VG. Maximum gain is set by external components, and the gain can be reduced all the way to cutoff. Power consumption is 110 mW with a speed of 150 MHz and a gain control bandwidth (BW) of 100 MHz. Output referred DC offset voltage is less than 55 mV over the entire gain control voltage range. Device-to-device gain matching is within 0.5 dB at maximum gain. Furthermore, gain is tested and guaranteed over a wide range. The output current feedback op amp allows high frequency large signals (Slew Rate = 1500 V/s) and can also drive a heavy load current (60 mA) guaranteed. Near ideal input characteristics (i.e. low input bias current, low offset, low pin 3 resistance) enable the device to be easily configured as an inverting amplifier as well. To provide ease of use when working with a single supply, the VG range is set to be from 0V to +2V relative to the ground pin potential (pin 4). VG input impedance is high in order to ease drive requirement. In single supply operation, the ground pin is tied to a "virtual" half supply. The LMH6505's gain control is linear in dB for a large portion of the total gain control range from 0 dB down to -85 dB at 25C, as shown below. This makes the device suitable for AGC applications. For linear gain control applications, see the LMH6503 datasheet. The LMH6505 is available in either the 8-Pin SOIC or the 8Pin MSOP package. The combination of minimal external components and small outline packages allows the LMH6505 to be used in space-constrained applications.
Features
VS = 5V, TA = 25C, RF = 1 k, RG = 100, RL = 100, AV = AVMAX = 9.4 V/V, Typical values unless specified. 150 MHz -3 dB BW 100 MHz Gain control BW 80 dB Adjustment range (<10 MHz) 0.50 dB Gain matching (limit) 7V to 12V Supply voltage range 1500 V/s Slew rate (inverting) 11 mA Supply current (no load) 60 mA Linear output current 2.4V Output voltage swing 4.4 nV/Hz Input noise voltage 2.6 pA/Hz Input noise current -45 dBc THD (20 MHz, RL = 100, VO = 2 VPP)
Applications

Variable attenuator AGC Voltage controlled filter Video imaging processing
Typical Application
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AVMAX = 9.4 V/V
Gain vs. VG
(c) 2007 National Semiconductor Corporation
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LMH6505
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 6) Human Body Model Machine Model Input Current Output Current (Note 3) Supply Voltages (V+ - V-) Voltage at Input/ Output pins Storage Temperature Range 2000V 200V 10 mA 120 mA 12.6V V+ +0.8V, V- -0.8V -65C to 150C (Note 2)
Junction Temperature Soldering Information: Infrared or Convection (20 sec) Wave Soldering (10 sec)
150C 235C 260C
Operating Ratings
Supply Voltages (V+ - V-) Temperature Range (Note 5) Thermal Resistance: 8 -Pin SOIC 8-Pin MSOP
(Note 1) 7V to 12V -40C to +85C (JC) 60 65 (JA) 165 235
Electrical Characteristics
Symbol Parameter
Unless otherwise specified, all limits are guaranteed for TJ = 25C, VS = 5V, AVMAX = 9.4 V/V, RF = 1 k, RG = 100, VIN = 0.1V, RL = 100, VG = +2V. Boldface limits apply at the temperature extremes. Conditions Min (Note 9) Typ (Note 8) 150 38 40 26 9.5 100 -51 80 71 2.1 10 Non Inverting Inverting Distortion & Noise Performance HD2 HD3 THD En tot IN DG DP GACCU G Match K 2nd Harmonic Distortion 3rd Harmonic Distortion f > 1 MHz, RSOURCE = 50 f > 1 MHz f = 4.43 MHz, RL = 100 Total Harmonic Distortion Total Equivalent Input Noise Input Noise Current Differential Gain Differential Phase Gain Accuracy (See Application Information) Gain Matching (See Application Information) Gain Multiplier (See Application Information) VG = 2.0V 0.8V < VG < 2V VG = 2.0V 0.8V < VG < 2V 0.890 0.830 2VPP, 20 MHz -47 -61 -45 4.4 2.6 0.30 0.15 0 +0.1/-0.53 -- -- 0.940 0.50 +4.3/-3.9 0.50 +4.2/-4.0 0.990 1.04 nV/ pA/ % deg dBc 900 1500 Max (Note 9) Units
Frequency Domain Response BW GF -3 dB Bandwidth Gain Flatness VOUT < 1 VPP VOUT < 4 VPP, AVMAX = 100 VOUT < 1 VPP 0.9V VG 2V, 0.2 dB Att Range Flat Band (Relative to Max Gain) Attenuation Range (Note 15) BW Control CT (dB) GR Gain control Bandwidth Feed-through Gain Adjustment Range 0.2 dB Flatness, f < 30 MHz 0.1 dB Flatness, f < 30 MHz VG = 1V (Note 4) VG = 0V, 30 MHz (Output/Input) f < 10 MHz f < 30 MHz Time Domain Response tr, tf OS % SR Rise and Fall Time Overshoot Slew Rate (Note 7) 0.5V Step ns % V/s dB MHz dB MHz MHz
dB
DC & Miscellaneous Performance dB dB V/V
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Symbol VIN NL VIN L I RG_MAX IBIAS TC IBIAS RIN CIN IVG TC IVG R VG C VG VOUT L VOUT NL ROUT IOUT VO OFFSET +PSRR -PSRR IS RG Current Bias Current
Parameter Input Voltage Range RG Open
Conditions
Min (Note 9) 0.60 0.50 6.0 5.0
Typ (Note 8) 3 0.74 7.4 -0.6 1.28 7 2.8 0.9 10 25 2.8
Max (Note 9)
Units
RG = 100 Pin 3 Pin 2 (Note 10) Pin 2 (Note 11) Pin 2 Pin 2 Pin 1, VG = 2V (Note 10) Pin 1 (Note 11) Pin 1 Pin 1 RL = 100 RL = Open Output Impedance Output Current Output Offset Voltage +Power Supply Rejection Ratio (Note 12) -Power Supply Rejection Ratio (Note 12) Supply Current DC VOUT = 4V from Rails 0V < VG < 2V Input Referred, 1V change, VG = 2.2V Input Referred, 1V change, VG = 2.2V No Load
V mA -2.5 -2.6
A nA/C M pF A pA/C M pF V
Bias Current Drift Input Resistance Input Capacitance VG Bias Current VG Bias Drift VG Input Resistance VG Input Capacitance Output Voltage Range
2.1 1.9
2.4 3.1 0.12 mA 55 70 mV dB
60 40
80 10
-65 -65 9.5 7.5
-72 -75 11 14 16
dB mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics. Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the Electrical Tables under conditions of internal self-heating where TJ > TA. Note 3: The maximum output current (IOUT) is determined by device power dissipation limitations or value specified, whichever is lower. Note 4: Gain control frequency response schematic:
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Note 5: The maximum power dissipation is a function of TJ(MAX), JA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ JA. All numbers apply for packages soldered directly onto a PC Board. Note 6: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
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Note 7: Slew rate is the average of the rising and falling slew rates. Note 8: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 9: Limits are 100% production tested at 25C. Limits over the operating temperature range are guaranteed through correlations using the Statistical Quality Control (SQC) method. Note 10: Positive current corresponds to current flowing into the device. Note 11: Drift is determined by dividing the change in parameter distribution at temperature extremes by the total temperature change. Note 12: +PSRR definition: [|VOUT/V+| / AV], -PSRR definition: [|VOUT/V-| / AV] with 0.1V input voltage. VOUT is the change in output voltage with offset shift subtracted out. Note 13: Gain/Phase normalized to low frequency value at 25C. Note 14: Gain/Phase normalized to low frequency value at each setting. Note 15: Flat Band Attenuation (Relative To Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain flatness specified (either 0.2 dB or 0.1 dB), relative to AVMAX gain. For example, for f < 30 MHz, here are the Flat Band Attenuation ranges: 0.2 dB: 19.7 dB down to -6.3 dB = 26 dB range 0.1 dB: 19.7 dB down to 10.2 dB = 9.5 dB range
Connection Diagram
8-Pin SOIC/MSOP
20171001
Top View
Ordering Information
Package 8-Pin SOIC 8-Pin MSOP Part Number LMH6505MA LMH6505MAX LMH6505MM LMH6505MMX Package Marking LMH6505MA AZ2A Transport Media 95 Units/Rail 2.5k Units Tape and Reel 1k Units Tape and Reel 3.5k Units Tape and Reel NSC Drawing M08A MUA08A
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Typical Performance Characteristics
Frequency Response Over Temperature
Unless otherwise specified: VS = 5V, TA = 25C, VG = VGMAX, RF = 1 k, RG = 100, VIN = 0.1V, input terminated in 50. RL = 100, Typical values. Frequency Response for Various VG
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Frequency Response (AVMAX = 2)
Inverting Frequency Response
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Frequency Response for Various VG (AVMAX = 100) (Large Signal)
Frequency Response for Various Amplitudes
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Gain Control Frequency Response
IS vs. VS
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IS vs. VS
Input Bias Current vs. VS
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PSRR
AVMAX vs. Supply Voltage
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Feed through Isolation for Various AVMAX
Gain Variation Over entire Temp Range vs. VG
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IRG vs. VIN
Gain vs. VG
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Output Offset Voltage vs. VG (Typical Unit #1)
Output Offset Voltage vs. VG (Typical Unit #2)
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LMH6505
Output Offset Voltage vs. VG (Typical Unit #3)
Distribution of Output Offset Voltage
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Output Noise Density vs. Frequency
Output Noise Density vs. Frequency
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Output Noise Density vs. Frequency
Input Referred Noise Density vs. Frequency
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Output Voltage vs. Output Current (Sinking)
Output Voltage vs. Output Current (Sourcing)
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Distortion vs. Frequency
HD vs. POUT
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THD vs. POUT
THD vs. POUT
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THD vs. Gain
THD vs. Gain
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Differential Gain & Phase
VG Bias Current vs. VG
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Step Response Plot
Step Response Plot
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Gain vs. VG Step
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Application Information
GENERAL DESCRIPTION The key features of the LMH6505 are: * Low power * Broad voltage controlled gain and attenuation range (from AVMAX down to complete cutoff) * Bandwidth independent, resistor programmable gain range (RG) * Broad signal and gain control bandwidths * Frequency response may be adjusted with RF * High impedance signal and gain control inputs The LMH6505 combines a closed loop input buffer ("X1" Block in Figure 1), a voltage controlled variable gain cell ("MULT" Block) and an output amplifier ("CFA" Block). The input buffer is a transconductance stage whose gain is set by the gain setting resistor, RG. The output amplifier is a current feedback op amp and is configured as a transimpedance stage whose gain is set by, and is equal to, the feedback resistor, RF. The maximum gain, AVMAX, of the LMH6505 is defined by the ratio: K * RF/RG where "K" is the gain multiplier with a nominal value of 0.940. As the gain control input (VG) changes over its 0 to 2V range, the gain is adjusted over a range of about 80 dB relative to the maximum set gain.
SETTING THE LMH6505 MAXIMUM GAIN
(1) Although the LMH6505 is specified at AVMAX = 9.4 V/V, the recommended AVMAX varies between 2 and 100. Higher gains are possible but usually impractical due to output offsets, noise and distortion. When varying AVMAX several tradeoffs are made: RG: determines the input voltage range RF: determines overall bandwidth The amount of current which the input buffer can source/sink into RG is limited and is given in the IRG_MAX specification. This sets the maximum input voltage: (2) As the IRG_MAX limit is approached with increasing the input voltage or with the lowering of RG, the device's harmonic distortion will increase. Changes in RF will have a dramatic effect on the small signal bandwidth. The output amplifier of the LMH6505 is a current feedback amplifier (CFA) and its bandwidth is determined by RF. As with any CFA, doubling the feedback resistor will roughly cut the bandwidth of the device in half. For more about CFAs, see the basic tutorial, OA-20, "Current Feedback Myths Debunked," or a more rigorous analysis, OA-13, "Current Feedback Amplifier Loop Gain Analysis and Performance Enhancements." OTHER CONFIGURATIONS 1) Single Supply Operation The LMH6505 can be configured for use in a single supply environment. Doing so requires the following: a) Bias pin 4 and RG to a "virtual half supply" somewhere close to the middle of V+ and V- range. The other end of RG is tied to pin 3. The "virtual half supply" needs to be capable of sinking and sourcing the expected current flow through RG. b) Ensure that VG can be adjusted from 0V to 2V above the "virtual half supply". c) Bias the input (pin 2) to make sure that it stays within the range of 2V above V- to 2V below V+. See the Input Voltage Range specification in the Electrical Characteristics table. This can be accomplished by either DC biasing the
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FIGURE 1. LMH6505 Typical Application and Block Diagram
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input and AC coupling the input signal, or alternatively, by direct coupling if the output of the driving stage is also biased to half supply. Arranged this way, the LMH6505 will respond to the current flowing through RG. The gain control relationship will be similar to the split supply arrangement with VG measured with reference to pin 4. Keep in mind that the circuit described above will also center the output voltage to the "virtual half supply voltage." 2) Arbitrarily Referenced Input Signal Having a wide input voltage range on the input (pin 2) (3V typical), the LMH6505 can be configured to control the gain on signals which are not referenced to ground (e.g. Half Supply biased circuits). This node will be called the "reference node". In such cases, the other end of RG which is the side not tied to pin 3 can be tied to this reference node so that RG will "look at" the difference between the signal and this reference only. Keep in mind that the reference node needs to source and sink the current flowing through RG. GAIN ACCURACY Gain accuracy is defined as the actual gain compared against the theoretical gain at a certain VG, the results of which are expressed in dB. (See Figure 2). Theoretical gain is given by:
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FIGURE 2. LMH6505 Gain Accuracy & Gain Matching Defined GAIN PARTITIONING If high levels of gain are needed, gain partitioning should be considered:
(3) Where K = 0.940 (nominal) N = 1.01V & VC = 79 mV at room temperature For a VG range, the value specified in the tables represents the worst case accuracy over the entire range. The "Typical" value would be the difference between the "Typical Gain" and the "Theoretical Gain." The "Max" value would be the worst case difference between the actual gain and the "Theoretical Gain" for the entire population.
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GAIN MATCHING As Figure 2 shows, gain matching is the limit on gain variation at a certain VG, expressed in dB, and is specified as "Max" only. There is no "Typical." For a VG range, the value specified represents the worst case matching over the entire range. The "Max" value would be the worst case difference between the actual gain and the typical gain for the entire population.
FIGURE 3. Gain Partitioning The maximum gain range for this circuit is given by the following equation:
(4) The LMH6624 is a low noise wideband voltage feedback amplifier. Setting R2 at 909 and R1 at 100 produces a gain of 20 dB. Setting RF at 1000 as recommended and RG at 50, produces a gain of about 26 dB in the LMH6505. The total gain of this circuit is therefore approximately 46 dB. It is important to understand that when partitioning to obtain high levels of gain, very small signal levels will drive the amplifiers to full scale output. For example, with 46 dB of gain, a 20 mV signal at the input will drive the output of the LMH6624 to 200 mV and the output of the LMH6505 to 4V. Accordingly, the designer must carefully consider the contributions of each stage to the overall characteristics. Through gain partitioning the designer is provided with an opportunity to optimize the frequency response, noise, distortion, settling time, and loading effects of each amplifier to achieve improved overall performance.
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LMH6505
LMH6505 GAIN CONTROL RANGE AND MINIMUM GAIN Before discussing Gain Control Range, it is important to understand the issues which limit it. The minimum gain of the LMH6505 is theoretically zero, but in practical circuits it is limited by the amount of feedthrough, here defined as the gain when VG = 0V. Capacitive coupling through the board and package, as well as coupling through the supplies, will determine the amount of feedthrough. Even at DC, the input signal will not be completely rejected. At high frequencies feedthrough will get worse because of its capacitive nature. At frequencies below 10 MHz, the feed through will be less than -60 dB and therefore, it can be said that with AVMAX = 20 dB, the gain control range is 80 dB. LMH6505 GAIN CONTROL FUNCTION In the plot, Gain vs. VG, we can see the gain as a function of the control voltage. The "Gain (V/V)" plot, sometimes referred to as the S-curve, is the linear (V/V) gain. This is a hyperbolic tangent relationship and is given by Equation 3. The "Gain (dB)" plots the gain in dB and is linear over a wide range of gains. Because of this, the LMH6505 gain control is referred to as "linear-in-dB." For applications where the LMH6505 will be used at the heart of a closed loop AGC circuit, the S-curve control characteristic provides a broad linear (in dB) control range with soft limiting at the highest gains where large changes in control voltage result in small changes in gain. For applications requiring a fully linear (in dB) control characteristic, use the LMH6505 at half gain and below (VG 1V). GAIN STABILITY The LMH6505 architecture allows complete attenuation of the output signal from full gain to complete cutoff. This is achieved by having the gain control signal VG "throttle" the signal which gets through to the final stage and which results in the output signal. As a consequence, the RG pin's (pin 3) average current (DC current) influences the operating point of this "throttle" circuit and affects the LMH6505's gain slightly. Figure 4 below, shows this effect as a function of the gain set by VG.
rent through RG would increase gain by 1.75 dB (to -58.25 dB). As you can see from Figure 4 above, the effect is most pronounced with reduced gain and is limited to less than 3.75 dB variation maximum. If the application is expected to experience RG DC current variation and the LMH6505 gain variation is beyond acceptable limits, please refer to the LMH6502 (Differential Linear in dB variable gain amplifier) datasheet instead at http:// www.national.com/ds/LM/LMH6502.pdf. AVOIDING OVERDRIVE OF THE LMH6505 GAIN CONTROL INPUT There is an additional requirement for the LMH6505 Gain Control Input (VG): VG must not exceed +2.3V (with 5V supplies). The gain control circuitry may saturate and the gain may actually be reduced. In applications where VG is being driven from a DAC, this can easily be addressed in the software. If there is a linear loop driving VG, such as an AGC loop, other methods of limiting the input voltage should be implemented. One simple solution is to place a 2.2:1 resistive divider on the VG input. If the device driving this divider is operating off of 5V supplies as well, its output will not exceed 5V and through the divider VG can not exceed 2.3V. IMPROVING THE LMH6505 LARGE SIGNAL PERFORMANCE Figure 5 illustrates an inverting gain scheme for the LMH6505.
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FIGURE 5. Inverting Amplifier The input signal is applied through the RG resistor. The VIN pin should be grounded through a 25 resistor. The maximum gain range of this configuration is given in the following equation:
(5) The inverting slew rate of the LMH6505 is much higher than that of the non-inverting slew rate. This 2X performance improvement comes about because in the non-inverting configuration the slew rate of the overall amplifier is limited by the input buffer. In the inverting circuit, the input buffer remains at a fixed voltage and does not affect slew rate. TRANSMISSION LINE MATCHING One method for matching the characteristic impedance of a transmission line is to place the appropriate resistor at the input or output of the amplifier. Figure 6 shows a typical circuit configuration for matching transmission lines.
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FIGURE 4. LMH6505 Gain Variation over RG DC Current Capability vs. Gain This plot shows the expected gain variation for the maximum RG DC current capability (4.5 mA). For example, with gain (AV) set to -60 dB, if the RG pin DC current is increased to 4.5 mA sourcing, one would expect to see the gain increase by about 3 dB (to -57 dB). Conversely, 4.5 mA DC sinking cur13
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FIGURE 6. Transmission Line Matching The resistors RS, RI, RO, and RT are equal to the characteristic impedance, ZO, of the transmission line or cable. Use CO to match the output transmission line over a greater frequency range. It compensates for the increase of the op amp's output impedance with frequency. MINIMIZING PARASITIC EFFECTS ON SMALL SIGNAL BANDWIDTH The best way to minimize parasitic effects is to use surface mount components and to minimize lead lengths and component distance from the LMH6505. For designs utilizing through-hole components, specifically axial resistors, resistor self-capacitance should be considered. For example, the average magnitude of parasitic capacitance of RN55D 1% metal film resistors is about 0.15 pF with variations of as much as 0.1 pF between lots. Given the LMH6505's extended bandwidth, these small parasitic reactance variations can cause measurable frequency response variations in the highest octave. We therefore recommend the use of surface mount resistors to minimize these parasitic reactance effects. RECOMMENDATIONS Here are some recommendations to avoid problems and to get the best performance: * Do not place a capacitor across RF. However, an appropriately chosen series RC combination can be used to shape the frequency response. * Keep traces connecting RF separated and as short as possible. * Place a small resistor (20-50) between the output and CL. * Cut away the ground plane, if any, under RG. * Keep decoupling capacitors as close as possible to the LMH6505. * Connect pin 2 through a minimum resistance of 25. ADJUSTING OFFSETS AND DC LEVEL SHIFTING Offsets can be broken into two parts: an input-referred term and an output-referred term. These errors can be trimmed using the circuit in Figure 7. First set VG to 0V and adjust the trim pot R4 to null the offset voltage at the output. This will eliminate the output stage offsets. Next set VG to 2V and adjust the trim pot R1 to null the offset voltage at the output. This will eliminate the input stage offsets.
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FIGURE 7. Offset Adjust Circuit DIGITAL GAIN CONTROL Digitally variable gain control can be easily realized by driving the LMH6505 gain control input with a digital-to-analog converter (DAC). Figure 8 illustrates such an application. This circuit employs National Semiconductor's eight-bit DAC0830, the LMC8101 MOS input op amp (Rail-to-Rail Input/Output), and the LMH6505 VGA. With VREF set to 2V, the circuit provides up to 80 dB of gain control in 256 steps with up to 0.05% full scale resolution. The maximum gain of this circuit is 20 dB.
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FIGURE 8. Digital Gain Control USING THE LMH6505 IN AGC APPLICATIONS In AGC applications, the control loop forces the LMH6505 to have a fixed output amplitude. The input amplitude will vary over a wide range and this can be the issue that limits dynamic range. At high input amplitudes, the distortion due to the input buffer driving RG may exceed that which is produced by the output amplifier driving the load. In the plot, THD vs. Gain, total harmonic distortion (THD) is plotted over a gain range of nearly 35 dB for a fixed output amplitude of 0.25 VPP in the specified configuration, RF = 1 k, RG = 100. When the gain is adjusted to -15 dB (i.e. 35 dB down from AVMAX), the input
amplitude would be 1.41 VPP and we can see the distortion is at its worst at this gain. If the output amplitude of the AGC were to be raised above 0.25 VPP, the input amplitudes for gains 40 dB down from AVMAX would be even higher and the distortion would degrade further. It is for this reason that we recommend lower output amplitudes if wide gain ranges are desired. Using a post-amp like the LMH6714/LMH6720/ LMH6722 family or the LMH6702 would be the best way to preserve dynamic range and yield output amplitudes much higher than 100 mVPP. Another way of addressing distortion performance and its limitations on dynamic range, would be to raise the value of RG. Just like any other high-speed amplifier, by increasing the load resistance, and therefore decreasing the demanded load current, the distortion performance will be improved in most cases. With an increased RG, RF will also have to be increased to keep the same AVMAX and this will decrease the overall bandwidth. It may be possible to insert a series RC combination across RF in order to counteract the negative effect on BW when a large RF is used. AUTOMATIC GAIN CONTROL (AGC) Fast Response AGC Loop The AGC circuit shown in Figure 9 will correct a 6 dB input amplitude step in 100 ns. The circuit includes a two op amp precision rectifier amplitude detector (U1 and U2), and an integrator (U3) to provide high loop gain at low frequencies. The output amplitude is set by R9. The following are some suggestions for building fast AGC loops: Precision rectifiers work best with large output signals. Accuracy is improved by blocking DC offsets, as shown in Figure 9.
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FIGURE 9. Automatic Gain Control Circuit
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Signal frequencies must not reach the gain control port of the LMH6505, or the output signal will be distorted (modulated by itself). A fast settling AGC needs additional filtering beyond the integrator stage to block signal frequencies. This is provided in Figure 9 by a simple R-C filter (R10 and C3); better distortion performance can be achieved with a more complex filter. These filters should be scaled with the input signal frequency. Loops with slower response time, which means longer integration time constants, may not need the R10 - C3 filter. Checking the loop stability can be done by monitoring the VG voltage while applying a step change in input signal amplitude. Changing the input signal amplitude can be easily done with an arbitrary waveform generator. CIRCUIT LAYOUT CONSIDERATIONS & EVALUATION BOARDS A good high frequency PCB layout including ground plane construction and power supply bypassing close to the package is critical to achieving full performance. The amplifier is sensitive to stray capacitance to ground at the I- input (pin 7) so it is best to keep the node trace area small. Shunt capacitance across the feedback resistor should not be used to compensate for this effect. Capacitance to ground should be minimized by removing the ground plane from under the body of RG. Parasitic or load capacitance directly on the output (pin 6) degrades phase margin leading to frequency response peaking.
The LMH6505 is fully stable when driving a 100 load. With reduced load (e.g. 1k.) there is a possibility of instability at very high frequencies beyond 400 MHz especially with a capacitive load. When the LMH6505 is connected to a light load as such, it is recommended to add a snubber network to the output (e.g. 100 and 39 pF in series tied between the LMH6505 output and ground). CL can also be isolated from the output by placing a small resistor in series with the output (pin 6). Component parasitics also influence high frequency results. Therefore it is recommended to use metal film resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not recommended. National Semiconductor suggests the following evaluation board as a guide for high frequency layout and as an aid in device testing and characterization: Device LMH6505 Package SOIC Evaluation Board Part Number LMH730066
The evaluation board can be shipped when a device sample request is placed with National Semiconductor. Evaluation board documentation can be found in the LMH6505 product folder at www.National.com.
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin SOIC NS Package Number M08A
8-Pin MSOP NS Package Number MUA08A
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LMH6505 Wideband, Low Power, Linear-in-dB, Variable Gain Amplifier
Notes
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